Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the photolithographic mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book Microchip Fabrication: A Practical Guide to Semiconductor Processing, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process is often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
As the technology advances in the semiconductor industry, the dimensions on a circuit have scaled down dramatically, which leads to significant deterioration in image quality and photolithography process robutstness. From a physical point of view, the ratio of the exposure wavelength over the numerical aperture of the imaging system needs to be reduced in order to improve the image fidelity. To enhance semiconductor device performance and to increase the chip functionality, the minimum feature size and minimum pitch on the chip designs have been reduced progressively in a very aggressive fashion. To meet the challenges, the semiconductor industry has developed exposure tools with shorter wavelengths and higher numerical apertures (NA). The continuous advances in photolithography exposure tools along this line have proven very successful until now. To further shorten the exposure wavelength beyond 193 nm or to further increase the numerical aperture beyond 0.9 presents enormous obstacles both economically and technically. To overcome the limitations imposed by the current photolithography exposure tool, the modification of mask data, which is commonly referred to as optical proximity correction (OPC), is gaining ever-increasing momentum in advanced photolithography. OPC usually consists of applying scattering bars (SBs), whose role is to enhance process latitude, and main feature biasing. The use of scatter bars is discussed in U.S. Pat. No. 5,242,770, herein incorporated by reference. Although scattering bar placement rules can be generated from optical imaging theory without taking the resist effect into account, the correct amount of biasing of the mask data at a given location can never be predicted accurately without considering the effect of the resist.
The original implementation of OPC is rule based, the rule set for a given process can be developed either through experiments or through a combination of optical modeling and resist modeling. The rule set thus obtained is essentially a look-up table from which the placement position of SB, if it is permitted, and the amount of correction for the main feature can be readily found, provided that the neighboring environment around the edge to be corrected can be specified. The neighboring environment considered in the rule based OPC is one-dimensional and short ranged. This character leads to its simplicity in implementation, but it also intrinsically sets the limitation of its accuracy. For 130 nm technology and beyond, the inadequacy of rule based OPC becomes evident, and new methods of OPC that can overcome the shortcomings of the rule based OPC is needed. The new method, for example, should provide a way to specify the 2-dimensional environment around the correction point on a much larger spatial scale.
For features having a pitch, where there is no room to insert SB, a typical method of optical proximity correction (OPC) is to adjust the feature edges (or apply bias) so that the printed feature width is closer to the intended width. In order for the use of the sub-resolution features and/or feature biasing to be effective for minimizing optical proximity effects, an operator having a substantial amount of knowledge regarding mask design and the printing process, as well as a substantial amount of experience, is required to modify the mask design to include the subresolution features and/or the adjustment of feature edges (biasing) if the desired goal is to be obtained. Indeed, even when an experienced operator performs this task, it is often necessary to conduct a “trial and error” process in order to properly position the subresolution features to obtain the desired corrections. This trial and error process, which can entail repeated mask revisions followed by repeated simulations, can become both a time consuming and costly process.
Current implementation for mask data biasing is commonly based on some model that has been calibrated on a specific photolithography process. Such an approach is commonly referred as to model OPC. For example, correcting for optical proximity effects (OPE) often entails attempting to “calibrate” the printing process so as to compensate for the OPEs. Currently known techniques include “correlating” so-called calibration parameters to the OPC model, which requires performing a set of detailed SEM CD measurements at various feature sites. Regardless of the actual feature shape, these are 1-dimensional width measurements. The more measurement data collected, the better the precision of the calibration parameters. However, for a reliable model parameter calibration, it is not unusual to require more than several hundreds of CD measurements at various critical feature sites under different neighboring environments. These are labor intensive and time consuming work. Worse, how the measurement CDs were taken can often become operator dependent due to the experience level, which can obviously impact the parameter calibration negatively, thereby limiting the overall effectiveness of the technique.
There are several ways to develop and implement model OPC, such as disclosed by John P. Stirniman, Michael L. Rieger, SPIE, Vol. 2197, (1994), 294 and Nick Cobb, Avideh Zakhor, and Eugene Miloslavsky, SPIE, Vol. 2726, (1996), 208. However, these models are facing ever-increasing challenges in meeting the more stringent dimension control requirements in low k1 photolithography. Those models are also very likely to fail in working with the new advanced photolithography technologies, such as Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. In addition to those concerns, advanced illuminations such as customer designed illuminators using diffractive optical elements (DOE), deviations of real illuminator profiles from theoretical top-hat illuminator profiles are all presenting enormous challenges to the current available models. To tackle the difficulties, a fundamentally different model, that has more solid physical and mathematical foundations, must be developed.
Various techniques exist to achieve illumination optimization for photolithography. Various mask optimization techniques also have been known. However, currently illumination optimization and mask optimization are not generally linked. U.S. Pat. No. 6,563,566 to Rosenbluth et al. discloses to perform illumination optimization and mask optimization through a series of calculations which attempt to linearize the optimization of the mask transmission. Rosenbluth discloses to maximize the minimum NILS (normalized image log slope) and to select various constraints to be used in the calculations. Rosenbluth also recognizes that the calculations may be limited relying on the symmetry of a mask. However, the linearization of the mask transmission used by Rosenbluth requires using several approximations in the calculations, instead of the actual imaging equations themselves, which produce errors in implementing a mask to form a desired image. The linearization of the mask transmission also requires the use of a significant number of variables, which requires significant computation time to perform the calculations. Accordingly, as logic feature sizes decrease, there is a need to provide mask implementations that precisely form a desired image with minimum computational time.